DocumentCode :
2688045
Title :
A 100 K gate sub-micron BiCMOS gate array
Author :
Gallia, J. ; Yee, A. ; Wang, I. ; Chau, K. ; Davis, H. ; Swamy, S. ; Sridhar, T. ; Nguyen, V. ; Ruparel, K. ; Moore, K. ; Lemonds, C. ; Chae, B. ; Eyres, P. ; Yoshino, T. ; Pozadzides, J. ; Rine, R. ; Shah, A.
fYear :
1989
fDate :
15-18 May 1989
Abstract :
A BiCMOS gate array in 0.8-μm technology has been developed with gate delays of 360 ps with a 0.4 pF load. A compact base cell (750 μm2/gate) has been designed with full bipolar drive capability. A 160 K-gate array has been built on a 1.14 cm square chip with ECL (emitter-coupled logic) I/O capability. Placing and routing in three levels of metal provide array utilization up to 92%. A description is given of the chip architecture and the implementation of a dual-cascode digital filter (74 K gates) with testability features such as JTAG and two-phase scan
Keywords :
BIMOS integrated circuits; digital filters; logic arrays; 0.8 micron; 360 ps; BiCMOS gate array; ECL; I/O capability; JTAG; array utilization; chip architecture; compact base cell; dual-cascode digital filter; full bipolar drive capability; gate delays; testability features; two-phase scan;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
Type :
conf
DOI :
10.1109/CICC.1989.56717
Filename :
5726184
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2688045
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