Synthesis of NoC Interconnects for Multi-core Architectures

As SoC applications demand high performance and integration density, SoC designers consider multiple aspects during the design phase. This paper presents a Network-on-Chip (NoC) design methodology for generating high quality interconnects for multi-core System-on-Chip architectures. The design process incorporates the main objectives of low power and high performance during topology synthesis. A rendezvous interaction performance analysis method is presented where Layered Queuing Network models are invoked to observe the asynchronous interactions between NoC components and identify possible performance degradation within the on-chip multi-core network. Several experiments are conducted using various SoC benchmark applications to compare the power and performance outcomes of our proposed technique.