DocumentCode
2688193
Title
A 2 K byte fully-associative cache memory with on-chip DRAM control
Author
Griffith, Scott ; Golson, Steve
fYear
1989
fDate
15-18 May 1989
Abstract
A 2 kbyte cache memory with on-chip DRAM (dynamic random-access memory) control has been built. The fully-associative write-back write-allocate cache is organized as 128 lines by 16 bytes. The part directly connects to and controls an array of 1 Mb DRAMs forming a 4 Mbyte parity-checked memory subsystem. Zero-wait-state operation of the Intel 80386 microprocessor at 25 MHz is supported. Fabricated in a 2 μm CMOS process, the 374-mil×383-mil die contains 172 K transistors
Keywords
CMOS integrated circuits; buffer storage; random-access storage; semiconductor storage; 1 Mbit; 2 kB; 2 micron; 4 MB; CMOS process; Intel 80386 microprocessor; fully-associative cache memory; on-chip DRAM control; write-back write-allocate cache; zero-wait-state operation;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location
San Diego, CA, USA
Type
conf
DOI
10.1109/CICC.1989.56727
Filename
5726194
Link To Document