A 1024-bit RSA cryptosystem hardware design based on modified Montgomery´s algorithm

A new version of Montgomery´s algorithm or modular multiplication of large integers is presented in this paper. And a 64-bit parallel carry look-ahead binary adder implemented by SRCMOS (self-resetting CMOS) circuits substitutes for the CPA and one of the two CSAs, which are needed in the previous implementation. And then we can get the modular multiplication result after the loop without the final comparison achieved by making the size of r two nits larger than that of N. In addition, SRCMOS circuits have lower power, faster switching speed and less area than equivalent static CMOS implementations, so we can get a high performance RSA cryptosystem.