An implementation method of a RSA crypto processor based on modified Montgomery algorithm

Author

Duoli Zhang ; Minglun Gao ; Li Li ; Xiaolei Wang

Author_Institution

Inst. of VLSI Design, Hefei Univ. of Technol., China

Volume

2

fYear

2003

fDate

21-24 Oct. 2003

Firstpage

1332

Abstract

In this paper, a new implementation method to optimize a 1024-bit RSA crypto processor is presented. By analyzing and improving high-radix Montgomery algorithm and FIPS method we propose a new algorithm that is suitable for signature card application. A corresponding RAM management approach is introduced. We have improved the former architecture of two multipliers computing in parallel so that the longest critical path of the whole design is greatly shortened. Performance analysis is performed. As a case study, a 1024-bit RSA crypto processor is implemented. The average operating time to calculate 1024-bit modular exponentiation is 1.58M cycles. Based on TSMC 0.25μm standard cell library, the synthesis gate count is about 36K and the highest frequency is 66M. At this speed, 1024-bit message encryption needs only 27.7ms.

Keywords

circuit optimisation; cryptography; logic design; microprocessor chips; multiplying circuits; 0.25 micron; 1024 bit; 27.7 ms; 66 MHz; FIPS method; RAM management approach; RSA crypto processor; TSMC; message encryption; modified Montgomery algorithm; modular exponentiation; performance analysis; signature card application; standard cell library;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2003. Proceedings. 5th International Conference on

ISSN

1523-553X

Print_ISBN

0-7803-7889-X

Type

conf

DOI

10.1109/ICASIC.2003.1277463

Filename

1277463