• DocumentCode
    2688480
  • Title

    Reliability processing of the circuits in CPLD design

  • Author

    Shaohui Cui ; Zhensheng Feng

  • Author_Institution
    Ordnance Eng. Coll., Shijiazhang, China
  • Volume
    2
  • fYear
    2003
  • fDate
    21-24 Oct. 2003
  • Firstpage
    1349
  • Abstract
    This paper studies on the elimination of the competitive and narrow pulse interference and on the reliability of the reset circuit in CPLD design. Methods of additional trigger, delay superposition, and large loop feedback are introduced. The corresponding examples are discussed detailedly. The reliability problems of the circuits in CPLD design are solved effectively.
  • Keywords
    integrated circuit reliability; interference (signal); logic design; programmable logic devices; CPLD design; FPGA; additional trigger; delay superposition; large loop feedback; pulse interference; reliability processing; reset circuit;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 2003. Proceedings. 5th International Conference on
  • ISSN
    1523-553X
  • Print_ISBN
    0-7803-7889-X
  • Type

    conf

  • DOI
    10.1109/ICASIC.2003.1277467
  • Filename
    1277467
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2688480