• DocumentCode
    2688526
  • Title

    iSPLICE3: a new simulator for mixed analog/digital circuits

  • Author

    Acuna, E.L. ; Dervenis, J.P. ; Pagones, A.J. ; Saleh, R.A.

  • fYear
    1989
  • fDate
    15-18 May 1989
  • Abstract
    A simulator called iSPLICE3 is described for the analysis of mixed analog/digital circuits is described. It combines electrical, switch-level timing and logic simulation modes using event-driven selective-trace techniques. This simulator features a hierarchical schematic capture package called iSPI for design entry and simulation control. It uses a novel approach to improve the speed and robustness of the DC solution. The details of the simulator architecture, circuit partitioning, mixed-mode interface, and event scheduling are provided along with the results of mixed-mode simulations of a recently designed memory circuit
  • Keywords
    circuit analysis computing; digital simulation; circuit partitioning; design entry; event scheduling; event-driven selective-trace techniques; hierarchical schematic capture package; iSPI; iSPLICE3; logic simulation modes; mixed analog/digital circuits; mixed model circuits; mixed-mode interface; mixed-mode simulations; simulation control; simulator; simulator architecture; switch-level timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
  • Conference_Location
    San Diego, CA, USA
  • Type

    conf

  • DOI
    10.1109/CICC.1989.56745
  • Filename
    5726212