Title :
Hierarchical timing view generation including accurate modeling for false paths
Author :
Das, P. ; Johannes, P. ; Claesen, L. ; De Man, H.
Abstract :
A hierarchical method for efficient solving the false path problem is presented. In a preprocessing step, all the local and user-intended logical incompatibilities are eliminated by generating timing views for these basic cells. These timing views are hierarchically composed, and there remain fewer (or no) logical incompatibilities. Therefore, the CPU-times required by the longest sensitizable path algorithm are much lower, and, for complex examples, this can mean a reduction of two orders of magnitude
Keywords :
circuit analysis computing; computational complexity; digital simulation; logic CAD; CPU-times required; accurate modeling for false paths; computational complexity reduction; false path problem; hierarchical method; hierarchical timing view generation; logical incompatibilities; longest sensitizable path algorithm; preprocessing step; reduction of two orders of magnitude; user-intended logical incompatibilities;
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/CICC.1989.56747
