Reliability assessment of transfer molded CSP

This paper describes the package and board level reliability assessment of a transfer molded chip scale package. Two chip scale package (CSP) designs have been developed, with a full matrix array of 144 I/Os and with 48 I/Os arranged in four rows. The assembly process takes advantage of existing packaging techniques and eliminates the need for new equipment and technology. The assembly process includes stencil wafer bumping followed by conventional packaging processes. The bumped dice were mounted on a metal frame and fully encapsulated by an epoxy mold compound. Openings in the encapsulation were created corresponding to the bumps on the die. These allow electrical testing and subsequent attachment to the PCB. At package level, the CSP is very robust. It passed the JEDEC moisture sensitivity level 1 test, 1000 cycles of temperature cycling at level G from -40 to 125°C and thermal shock test at level D from -65 to 150°C. At board level, flip-chip and CSP were assembled for reliability comparison. In the temperature humidity test, all legs passed 1000 hr at 85°C/85% RH. As for temperature cycling test, both bare flip-chip and CSP on board experienced early failures when not underfill encapsulated. When underfill encapsulated, the CSP on board is more reliable than the bare flip-chip on board