Principle of operation and performance of 1.3 volt SOI resistor load vertical dual carrier field effect transistor flip flop fabricated for SRAM, FPGA and switching SOC with effective channel length of 30nm

Author

Tang, Z.M. ; Li, G.H. ; Yang, Roger ; Yang, Young Hwi ; Han, D.J. ; Huang, D.H. ; Lin, C.L. ; Xu, Y.Z. ; Xu, Peng ; Zhang, J.C. ; Wu, C.L. ; Yan, F.Z. ; Ren, Y.L. ; Yu, L.K. ; Cai, I.M. ; Tian, X.N. ; Du, S.C. ; Huang, Chao

Author_Institution

Inst. of Comput. Technol., CAS, Beijing, China

Volume

2

fYear

2003

fDate

21-24 Oct. 2003

Firstpage

1373

Abstract

Principle of operation of resistor load SOI vertical dual carrier field effect transistor (VDCFET) flip flop is reviewed. The measured and the calculated results of the performance of the 1.3 volt resistor load SOI VDCFET flip flop, with 30nm effective channel length, are presented. These SOI VDCFET flip-flops are fabricated by using lithographic equipments for linewidths greater than 180nm. These flip flops are being designed as the main building blocks of VDCFET SRAM, FPGA and switching SOC with effective channel length of 30nm.

Keywords

SRAM chips; field effect transistors; field programmable gate arrays; flip-flops; logic simulation; silicon-on-insulator; system-on-chip; 1.3 V; 30 nm; FPGA; SOI resistor load; SRAM; VDCFET; channel length; flip flop; lithographic equipments; switching SOC; vertical dual carrier field effect transistor;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2003. Proceedings. 5th International Conference on

ISSN

1523-553X

Print_ISBN

0-7803-7889-X

Type

conf

DOI

10.1109/ICASIC.2003.1277473

Filename

1277473