Reliability challenges and design considerations for Wafer-Level packages

Wafer-level packaging (WLP) is essentially a true chip-scale packaging (CSP) technology, since the resulting package is practically of the same size as the die. Furthermore, wafer-level packaging paves the way for true integration of wafer fab, packaging, test, and burn-in at wafer level, for the ultimate streamlining of the manufacturing process undergone by a device from silicon start to customer shipment. There are several WLP technology classifications. Redistribution layer and bump technology, the most widely-used WLP technology, extends the conventional wafer fab process with an additional step that deposits a multi-layer thin-film metal rerouting and interconnection system to each device on the wafer. In this paper, an overview of the state of art WLP packaging technologies will be presented. The emphasis will be given to the challenges in reliability and the solutions based on the design.