Modeling techniques for board level drop test for a wafer-level package

Reliability performance during drop impact is critical for electronic handheld devices. In this paper, a comprehensive study in efficiency and accuracy of multiple finite element modeling approaches and solution techniques for a wafer-level package (WLP) is presented. JEDEC specified test board is used for the model study. A direct acceleration input method is introduced. Two types of global finite element models for a typical WLP are studied: solder layer and solder bump models. Two different approaches, full implicit dynamics and mode superposition, are applied to solve the JEDEC board dynamic responses. Based on this study, the 8-node solid element with smeared solder layer model, and the full implicit dynamics with either input-G or direct acceleration method are recommend. This combination results in short solution time and produces accurate dynamic solutions for drop test board. It has been found that the fundamental natural frequency of a JEDEC board with WLP typically ranges from 200 to 250 Hz for a large range of array size. There is a large strain gradient close to the component edge for each package on the test board. Due to the rigidity of the silicon chip, the board strain at the center of each component on the opposite side of PCB does not reflect the local bending behaviors of the board. The center of the board between two components might be a stationary point, which does not capture the board bending. With the increase of the chip size, the board strain at edge of each component will increase. The board peak strain at the corner package (U1, U5, U11, and U15) has been found greater than that at the center package (U8), but the bending direction is opposite. The components U6 and U10 have lowest board strains among all components.