Design of a switching node (router) for on-chip networks

Author

Sathe, Saket ; Wiklund, D. ; Liu, Deming

Author_Institution

Dept. of Electr. Eng., Linkoping Univ., Sweden

Volume

1

fYear

2003

fDate

21-24 Oct. 2003

Firstpage

75

Abstract

Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional interconnects, such as on-chip networks (OCN), must be used. Our OCN is capable of providing a data transfer throughput of 19.2 Gbps/link. The key element of our OCN is the switching node. We present a prototype design of a 5-input, 5-output, scalable switching node. The switching node is constructed from a collection of parameterizable and reusable hardware blocks, and is a basic building block of our OCN. The switching node is characterized by an area of 0.06 mm sq. and a frequency of 1.2 GHz in 0.18 micron CMOS technology.

Keywords

CMOS integrated circuits; integrated circuit interconnections; network routing; switching networks; system-on-chip; 1.2 GHz; 19.2 Gbit/s; CMOS technology; OCN; compositional interconnects; decoupling computation; hardware blocks; on-chip networks; prototype design; router design; scalable interconnects; switching node design;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2003. Proceedings. 5th International Conference on

ISSN

1523-553X

Print_ISBN

0-7803-7889-X

Type

conf

DOI

10.1109/ICASIC.2003.1277494

Filename

1277494