Plastic package related effects, measured by means of silicon test patterns

The authors present three different advanced test vehicles that help ICs and the package engineers involved in the design and development of new devices. The first is a silicon integrated circuit for mechanical stress evaluation; the second is a special metal pattern for passivation layer characterization and device metal displacement evaluation; and the last is an integrated structure for package thermal characterization. These techniques are designed to measure and quantify the effect of plastic packaging on silicon devices.<>