Measurement of stress and temperature distribution in large area dies

A method for the measurement of strain and temperature distribution in mounted silicon chips has been developed and successfully demonstrated. Generally, the results obtained confirmed predictions qualitatively but quantitatively showed considerable variance with theoretical models. The stress induced in dies as a result of epoxy bonding is typically a factor of 5 lower than predicted. The stress induced in solder-bonded dies is minimal. In general, the degree of stress induced in chips is proportional to the thermal expansion coefficient of the substrate, but the mechanical compliance, thickness, and homogeneity of the die bonding material are also of critical importance. The temperature distribution in locally heated silicon mounted on different substrate types is dependent upon heat dissipation, the proximity of the heat source, the efficiency of the thermal conduction route from the dies, and the thermal conductivity of the substrate. The results demonstrate the inadequacy of current modeling methods and the need for direct measurement of strain and temperature in VLSI die bonding and thermal assessment.<>