Exploring microprocessor architectures for gigascale integration

As VLSI advances towards billions of fast transistors on a chip (Gigascale Integration, or GSI), it is becoming clear that interconnect issues will dominate. Conventional uniprocessor architectures, developed in an era when interconnect was largely ignored, may be incompatible with this technology. This paper presents a quantitative exploration of architectural alternatives for gigascale technology. It evaluates a set of candidate architectures in 100 nm technology that span a spectrum of uniprocessor and multiprocessor configurations. Results show that a system composed of a small number of moderately complex processors provides the best performance over a wide range of applications. Designs that include large complex uniprocessors are limited by wire delay, and fall short of parallel systems when even a small amount of explicit parallelism is available (greater than 10% of the workload). Similarly, highly parallel designs with many small processors are restricted in sequential environments with limited parallelism. The only designs capable of maintaining Moore´s law require extremely parallel workloads.