An advanced design system: design capture, functional test generation, mixed level simulation and logic synthesis [VLSI]

Author

Sekine, Masakazu ; Ueda, Shoji ; Kogure, Makoto ; Takei, Tsutomu ; Aihara, M. ; Yano, Eiichi ; Iwawaki, K. ; Yamagishi, Kunihiko ; Kohno, Kazuyoshi ; Kitahara, Takeshi ; Fukasawa, Takayuki

fYear

1989

fDate

15-18 May 1989

Abstract

A VLSI CAD (computer-aided design) system has been enhanced by adding several tools. It consists of a mixed-level simulator, logic synthesis, layout systems, a functional test generation assistance, etc. The functional simulator, which is on a laptop PC, is for a 50 K-gate class LSI, and the mixed level simulator, which is on an EWS and a mainframe, is for above-100 K-gate VLSI. In-house designer groups have reported that the design time is cut in half using the system. A functional schematic capture provides a more friendly user interface than a logic schematic capture. A novel approach to functional test generation is also provided

Keywords

VLSI; circuit CAD; circuit analysis computing; circuit layout CAD; digital simulation; integrated circuit testing; logic CAD; logic testing; microcomputer applications; CAD system; EWS; VLSI; advanced design system; computer-aided design; design capture; friendly user interface; functional schematic capture; functional test generation; laptop PC; layout systems; logic synthesis; mainframe; mixed level simulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989

Conference_Location

San Diego, CA, USA

Type

conf

DOI

10.1109/CICC.1989.56789

Filename

5726256