Title :
A fully integrated design methodology for 100 K-gate CMOS custom LSIs with TAB packaging
Author :
Yamamura, Takeshi ; Kuwano, Kazusumi ; Sugatani, Shinji ; Tsujimura, Takehisa
Abstract :
A fully integrated design methodology based on a 1.0-μm CMOS standard cell technology with tape automated bonding (TAB) packaging has been developed to design and fabricate maximum 100 K-gate custom LSIs. The methodology has been successfully applied to the design of an I/O control processor. The processor was fabricated and housed in a 321-pin PGA (pin-grid-array)-type TAB package
Keywords :
CMOS integrated circuits; VLSI; application specific integrated circuits; packaging; 1 micron; CMOS standard cell technology; I/O control processor; TAB packaging; custom LSIs; integrated design methodology; monolithic IC; pin-grid-array; tape automated bonding;
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/CICC.1989.56791
