• DocumentCode
    2689647
  • Title

    A 1.0 μm compilable FIFO buffer for standard cell

  • Author

    Kawauchi, Masaharu ; Haraguchi, Masanori ; Okada, Yoshinori ; Tanaka, Yutaka ; Suzuki, Hiroaki

  • fYear
    1989
  • fDate
    15-18 May 1989
  • Abstract
    A compilable first-in-first-out (FIFO) buffer cell has been developed using a module generator with routing capability. The cell has a capability of compiling up to 2048 words×9 bits (a minimum of 16 words×4bits). In a 1.0-μm CMOS technology, a read/write cycle time of 20 ns (50 MHz) can be achieved at the maximum words and bits
  • Keywords
    CMOS integrated circuits; buffer storage; circuit CAD; circuit layout CAD; integrated memory circuits; 1 micron; 20 ns; 50 MHz; CAD; CMOS technology; compilable FIFO buffer; computer aided design; first-in-first-out; megacell generator; memory IC; module generator; read/write cycle time; routing capability; standard cell;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
  • Conference_Location
    San Diego, CA, USA
  • Type

    conf

  • DOI
    10.1109/CICC.1989.56817
  • Filename
    5726284
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2689647