A 2.4 μm CMOS switched-capacitor video decimator with sampling rate reduction from 40.5 MHz to 13.5 MHz

A description is given of the design and integrated-circuit implementation of a fifth-order elliptic lowpass switched-capacitor (SC) video decimator with a cutoff frequency of 3.6 MHz and sampling rate reduction from 40.5 MHz to 13.5 MHz. A recently proposed decimator architecture used to make the settling time requirements of the operational amplifiers similar to those of a conventional SC filter with switching frequency of only 13.5 MHz. The circuit is implemented using a 2.4-μm CMOS double-poly process yielding a total area of less than 1 mm². The power consumption is less than 50 mW with a 10-V power supply