Title :
Limitations of the stuck-at fault model as an accurate measure of CMOS IC quality and a proposed schematic level fault model
Abstract :
Limitations in current testability approaches have forced major compromises in IC fault modeling, test, and quality. The stuck-at fault model is inadequate to achieve very high quality. Meaningful CMOS fault models based on schematically extracted faults are presented. Unity observability, the ability to probe all nodes, is presented as a practical approach to effective use of these models
Keywords :
CMOS integrated circuits; fault location; integrated circuit testing; logic testing; CMOS IC; IC fault modeling; defect models; logic testing; quality assessment; schematic level fault model; schematically extracted faults; stuck-at fault model; unity observability;
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/CICC.1989.56836
