Design of high speed 2write/6read eight-port register file

This paper gives a delay model of the register files which are made of multi-port SRAM technology. Then we realized a 32word×32 bit 2write/6read eight-Port register files. During the realization, according to the presenting delay model, we present a grouping wordline method to reduce the delay time of register files, also there are some structure modifying for the storage cells of register files. With the 2.5 v 0.25 μm CMOS technology, simulation results show that delay time of the register file is reduced by 11.5% than the register file which hasn´t adopted novel method.