DocumentCode
2690759
Title
Design of a Novel FET Frequency Doubler Using a Harmonic Balance Algorithm
Author
Gilmore, R.
fYear
1986
fDate
2-4 June 1986
Firstpage
585
Lastpage
588
Abstract
The design of a wideband FET frequency doubler operating with a 4-8 GHz input bandwidth is described. The doubler and bandreject amplifier combination achieve an average conversion loss of 3.5 dB across the 8-16 GHz output band. The design method uses the harmonic balance algorithm implemented on an IBM PC-AT personal computer.
Keywords
Algorithm design and analysis; Bandwidth; Circuit analysis; Design optimization; FETs; Frequency; Linear circuits; Nonlinear equations; Voltage; Wideband;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Symposium Digest, 1986 IEEE MTT-S International
Conference_Location
Baltimore, MD, USA
ISSN
0149-645X
Type
conf
DOI
10.1109/MWSYM.1986.1132253
Filename
1132253
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