Title :
Design of a Novel FET Frequency Doubler Using a Harmonic Balance Algorithm
Abstract :
The design of a wideband FET frequency doubler operating with a 4-8 GHz input bandwidth is described. The doubler and bandreject amplifier combination achieve an average conversion loss of 3.5 dB across the 8-16 GHz output band. The design method uses the harmonic balance algorithm implemented on an IBM PC-AT personal computer.
Keywords :
Algorithm design and analysis; Bandwidth; Circuit analysis; Design optimization; FETs; Frequency; Linear circuits; Nonlinear equations; Voltage; Wideband;
Conference_Titel :
Microwave Symposium Digest, 1986 IEEE MTT-S International
Conference_Location :
Baltimore, MD, USA
DOI :
10.1109/MWSYM.1986.1132253
