DocumentCode
2690858
Title
Parallelization of H.264 video decoder for embedded multicore processor
Author
Nishihara, Kosuke ; Hatabu, Atsushi ; Moriyoshi, Tatsuji
Author_Institution
Syst. IP Core Res. Labs., NEC Corp., Tokyo
fYear
2008
fDate
June 23 2008-April 26 2008
Firstpage
329
Lastpage
332
Abstract
This paper presents two parallelization methods for H.264 video decoder software on an embedded multicore processor. In parallelizing the H.264 video decoder software on a typical embedded multicore processor with shared memory, there are two problems. One problem is the computational load imbalance among cores. The other problem is memory access contention. The first method is coarse, flexible partitioning adapted for the H.264 decoding functions, which can balance the load with only a small number of synchronizations. The second method is preloading based on predicting the execution time, which can reduce memory access contention and the redundant waiting time for other cores. Experimental results demonstrate that our proposed two methods can achieve significant improvement of the consumed cycles for decoding H.264 bitstreams of QVGA size from 217 to 96 Mcps (2.3 times speedup) as compared to a non-parallel decoder.
Keywords
decoding; digital signal processing chips; embedded systems; logic partitioning; parallel programming; resource allocation; shared memory systems; synchronisation; video coding; H.264 video decoder software; embedded multicore processor; load balancing; logic partitioning; memory access contention; parallelization method; shared memory system; synchronization; Decoding; Multicore processing; H.264; decoder; multicore processor; parallelization;
fLanguage
English
Publisher
ieee
Conference_Titel
Multimedia and Expo, 2008 IEEE International Conference on
Conference_Location
Hannover
Print_ISBN
978-1-4244-2570-9
Electronic_ISBN
978-1-4244-2571-6
Type
conf
DOI
10.1109/ICME.2008.4607438
Filename
4607438
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