Wideband multi-bit third-order sigma-delta ADC for wireless transceivers

This paper presents a multi-bit sigma-delta data converter with third-order 3-bit topology. This converter can achieve high resolution with a lower order modulator and lower oversampling ratio than single-bit converter. The dynamic element matching (DEM) algorithm is designed in such a way as to minimize delay within the feedback loop of the sigma-delta ADC. The behavioral model is used to simulate the designed sigma-delta data converter. The designed ADC achieves 14-bit resolution, a peak SNR of 87dB within a 1 MHz signal baseband at a clock rate of 50MHz.