Title :
High-resolution low-power CMOS D/A converter
Author :
Yang, John W. ; Martin, Kenneth W.
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
A very low-power, high-resolution, medium-speed D/A (digital-to-analog) converter is described. The converter was realized using a standard analog CMOS technology. It achieved 15 bits monotonicity and less than 0.7% overall linearity at a clock frequency of 100 kHz, without requiring any trimming or calibration. The measured SNR (signal-to-noise ratio) was 85 dB, and the measured power dissipation was less than 10 mW
Keywords :
CMOS integrated circuits; digital-analogue conversion; SNR; clock frequency; freq 100 kHz; high-resolution; linearity; low-power CMOS D/A converter; monotonicity; power dissipation; signal-to-noise ratio; standard analog CMOS technology; CMOS technology; Calibration; Capacitors; Clocks; Control system synthesis; Frequency; Linearity; Operational amplifiers; Speech synthesis; Voltage;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo
DOI :
10.1109/ISCAS.1988.15525
