A 40nm low power SRAM retention circuit with PVT-aware self-refreshing virtual VDD regulation

Author

Dray, Cyrille ; Badereddine, Nabil ; Chanussot, Christophe

Author_Institution

Infineon Technol. France, Sophia-Antipolis, France

fYear

2010

fDate

16-19 May 2010

Firstpage

1

Lastpage

4

Abstract

This paper describes an integrated SRAM standby power reduction design in a 40 nm low power process. It features a closed-loop array leakage control with floating bitlines, reducing 46% of leakage current. It relies on self-refreshing virtual VDD clocked by a PVT-compensated SRAM worst-case data retention sensor. The concept is implemented in a 256 kbit SRAM with a 0.242μm² 6T cell.

Keywords

SRAM chips; compensation; leakage currents; low-power electronics; voltage regulators; PVT-aware self-refreshing virtual VDD regulation; PVT-compensated SRAM worst-case data retention sensor; closed-loop array leakage control; integrated SRAM standby power reduction design; leakage current; low power SRAM retention circuit; process-voltage-temperature compensation; size 40 nm; storage capacity 256 Kbit; Circuits; Clocks; Dynamic voltage scaling; Energy consumption; Energy management; Frequency; Leakage current; Random access memory; Regulators; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop (IMW), 2010 IEEE International

Conference_Location

Seoul

Print_ISBN

978-1-4244-6719-8

Electronic_ISBN

978-1-4244-7668-8

Type

conf

DOI

10.1109/IMW.2010.5488323

Filename

5488323