Optimized Scalable Hardware Architecture for Modular Addition and Subtraction in Dual-Field

Modular addition and subtraction are applied in every public key cryptography (PKC), such as RSA and ECC. But they are time consuming operations with delay of long carry and borrow propagations when the operands are great numbers. An optimized scalable and unified hardware architecture is proposed in this paper to work with any precision operands for both prime and binary extension finite fields, and modular addition and subtraction are integrated into one single hardware architecture. For obtaining performance results, our work is captured in VerilogHDL and implemented under 0.18 mum CMOS technology. The results indicate that the scalable and unified hardware architecture in our work can work at high clock frequency compared with fixed designs when the operands are large number, and the clock frequency is falling slowly while the width of data path is increasing.