Title :
H.264/AVC motion estimation implmentation on Compute Unified Device Architecture (CUDA)
Author :
Chen, Wei-Nien ; Hang, Hsueh-Ming
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu
fDate :
June 23 2008-April 26 2008
Abstract :
Due to the rapid growth of graphics processing unit (GPU) processing capability, using GPU as a coprocessor to assist the central processing unit (CPU) in computing massive data becomes essential. In this paper, we present an efficient block-level parallel algorithm for the variable block size motion estimation (ME) in H.264/AVC with fractional pixel refinement on a computer unified device architecture (CUDA) platform, developed by NVIDIA in 2007. The CUDA enhances the programmability and flexibility for general-purpose computation on GPU. We decompose the H.264 ME algorithm into 5 steps so that we can achieve highly parallel computation with low external memory transfer rate. Experimental results show that, with the assistance of GPU, the processing time is 12 times faster than that of using CPU only.
Keywords :
coprocessors; motion estimation; parallel algorithms; video coding; CUDA; GPU; H.264-AVC motion estimation; NVIDIA; block-level parallel algorithm; computer unified device architecture; coprocessor; fractional pixel refinement; graphics processing unit; variable block size motion estimation; Automatic voltage control; Central Processing Unit; Computer architecture; Computer displays; Concurrent computing; Graphics; Motion estimation; Random access memory; Read-write memory; Samarium; Compute Unified Device Architecture (CUDA); Graphics Processing Unit (GPU); H.264/AVC; Motion Estimation; Parallel Processing;
Conference_Titel :
Multimedia and Expo, 2008 IEEE International Conference on
Conference_Location :
Hannover
Print_ISBN :
978-1-4244-2570-9
Electronic_ISBN :
978-1-4244-2571-6
DOI :
10.1109/ICME.2008.4607530
