3D IC architecture for high density memories

Memory device scaling is facing increasing challenges due to the limited number of read and write cycles in flash memories, capacitor scaling limitations for DRAM cells, high lithography manufacturing costs, and low return-on-investment (ROI) from fab investments. Hence, emerging memories, based on new materials and concepts are being developed. However, material breakthroughs must be realized for these emerging memories to be successful before market introduction. Among potential candidates are phase-change and resistive memories. The scalability of ferroelectric and magnetic RAM is poor and unlikely to meet future scaling challenges. To overcome these challenges, low-cost and high-density memory cell stacking in 3-dimensional (3D) integrated circuits (ICs) is desirable. Unlike well-known 3D through-silicon-vias (TSV) a package-level technology the true 3D IC, or simply 3D IC, must be able to stack multi-memory layers sequentially on top of other device layers in a single chip at low cost using proven materials and devices. We propose such an approach and have developed the relevant technology to bring about this memory evolution.