Future evolution of memory subsystem in mobile applications

As smart phones make for the focal point of today´s ubiquitous computing, demands of increased memory performance for DRAM and Flash storage are surging while trying to suppress power consumption. New DRAM architectures such as Wide IO, serial I/O and combo are investigated in the industry. Fast read/write access to Flash storage is needed with the virtual memory system under multi-tasking. This paper discusses new DRAM architectures from the perspective of performance, power consumption, pin counts and others. The performance enhancement of Flash storage is discussed in optimizing the internal device for the system access pattern, and on the requirements of system software and storage interface scheme for dealing with multiple access queues.