Double-gate MOSFETs with aymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM

Over the past few decades, CMOS technology has mainly been driven by transistor scaling. However, the scaling benefits of conventional bulk MOSFETs come at the cost of increased short channel effects, degrading their performance as a switch. In order to counter such effects, device structures with enhanced gate control of the channel have been proposed. A double-gate (DG) MOSFET is one such structure which has shown tremendous promise. Due to reduced junction capacitance in DG-MOSFETs, drain capacitance is mainly dominated by the overlap capacitance, which may be reduced by introducing an underlap between source/drain and channel. However, underlap on the source side leads to significant degradation in ON-current as well as increased effect of process variations on the threshold voltage. Hence, in this paper, we explore the design and optimization of DG-MOSFETs with underlap only on the drain side.