DocumentCode
2692754
Title
Deep sub-micron and self-aligned flatband III–V MOSFETs
Author
Hill, R.J.W. ; Li, X. ; Zhou, H. ; Macintyre, D.S. ; Thoms, S. ; Holland, M.C. ; Longo, P. ; Moran, D.A.J. ; Craven, A.J. ; Stanley, C.R. ; Asenov, A. ; Droopad, R. ; Passlack, M. ; Thayne, I.G.
Author_Institution
Nanoelectron. Res. Centre, Univ. of Glasgow, Glasgow, UK
fYear
2009
fDate
22-24 June 2009
Firstpage
251
Lastpage
252
Abstract
In conclusion, this paper reports a number of significant developments in III-V MOSFET devices. Retaining a subthreshold slope of 60-70 mV/decade for gate lengths down to 100 nm with an EOT of 3.4 nm shows for the first time that the flatband mode device architecture is tolerant to short channel effects. In addition, a generic silicon compatible process flow for the realization of fully self-aligned III-V MOSFETs has been demonstrated and shown capable of realizing 100 nm gate length enhancement mode devices.
Keywords
III-V semiconductors; MOSFET; elemental semiconductors; silicon; EOT; deep sub-micron; self-aligned flatband III-V MOSFET devices; short channel effects; size 100 nm; Dielectrics; Displays; Geometry; Gold; III-V semiconductor materials; Interface states; MOSFETs; Nanoelectronics; Silicon; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Device Research Conference, 2009. DRC 2009
Conference_Location
University Park, PA
Print_ISBN
978-1-4244-3528-9
Electronic_ISBN
978-1-4244-3527-2
Type
conf
DOI
10.1109/DRC.2009.5354900
Filename
5354900
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