Double-self-aligned short-channel power DMOSFETs in 4H-SiC

Silicon carbide power DMOSFETs have made significant advances in recent years, demonstrating blocking voltages as high as 10 kV and absolute on-currents greater than 20 A on a single device. As currents and voltages have increased, there has been a simultaneous effort to reduce the specific on-resistance R_ONSP to enable SiC DMOSFETs to compete in the 600-1,800 V regime, where the market demand is large. Several innovations have contributed to a reduction in on-resistance, including a self-aligned process for short (0.3-0.5 ¿m) MOSFET channels, narrow heavily-doped JFET regions and n-type current spreading layers to reduce JFET resistance, segmented base contacts to increase source contact area, and advances in postoxidation annealing that increase inversion layer mobilities. Recent optimization studies indicate that in the latest 1 kV-class DMOSFETs, on-resistance is limited almost equally by contributions from the source, the inversion channel, and the JFET region. In this paper, we describe a method to reduce cell pitch (and hence R_ONSP) using a self-aligned source contact. This technique, when combined with the self-aligned short-channel process, results in a double-self-aligned structure that exhibits the lowest R_ONSP yet reported for 1 kV DMOSFETs.