Title :
Multi-layer graphene field-effect transistors for improved device performance
Author :
Sui, Yang ; Appenzeller, Joerg
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
We have noticed the importance of noise impacting the performances of nano-patterned graphene FETs. We performed the first experimental study on multi-layer graphene FETs to address the charge and current distribution. We have developed a model describing the coupling between graphene layers including interlayer screening effects. The model does not involve modification of the band structure for multiple-layer graphene. The model is in good agreement with the experimental results as well as previous studies on intercalated graphite structures. Noise reduction in few-layer graphene FETs can be understood within this model as well. For the above reason, we propose two or three-layer graphene to be a better choice for aggressively nano-patterned devices.
Keywords :
field effect transistors; semiconductor device models; charge distribution; current distribution; graphene layers; interlayer screening effects; multi-layer graphene field-effect transistors; multiple-layer graphene; nano-patterned devices; nano-patterned graphene FET; noise reduction; Current distribution; Displays; FETs; High performance computing; Nanoscale devices; Nanotechnology; Noise reduction; Physics computing; Power engineering and energy; Temperature;
Conference_Titel :
Device Research Conference, 2009. DRC 2009
Conference_Location :
University Park, PA
Print_ISBN :
978-1-4244-3528-9
Electronic_ISBN :
978-1-4244-3527-2
DOI :
10.1109/DRC.2009.5354950