DocumentCode
2693894
Title
Silicon compiler for neuro-ASICs
Author
Ouali, J. ; Saucier, G.
fYear
1990
fDate
17-21 June 1990
Firstpage
557
Abstract
A distributed, synchronous architecture for artificial neural networks is proposed. A basic processor is associated to a neuron and is able to perform autonomously all the steps of the learning and the relaxation phases. Data circulation is implemented by shifting techniques. Customization of the network is done by setting identification data in dedicated memory elements. The neuron has been implemented on silicon. It is shown that, in a silicon compiler environment, dedicated networks can be easily generated by cascading these elementary blocks
Keywords
application specific integrated circuits; circuit layout CAD; neural nets; parallel architectures; activation function; artificial neural networks; cascadable neuron processor; dedicated memory elements; finite state machine compiler; identification data; learning algorithm; neuro-ASIC; relaxation phases; silicon compiler environment; synchronous distributed architecture;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks, 1990., 1990 IJCNN International Joint Conference on
Conference_Location
San Diego, CA, USA
Type
conf
DOI
10.1109/IJCNN.1990.137627
Filename
5726587
Link To Document