Turn-on transient analysis of a BiPMOS device

Author

Kuo, J.B. ; Rosseel, G.P. ; Dutton, R.W.

Author_Institution

Stanford Univ., CA, USA

fYear

1989

fDate

17-19 May 1989

Firstpage

94

Lastpage

97

Abstract

A BiPMOS device based on a 2-μm BiCMOS technology with a buried layer and a 0.8-μm 1×10¹⁶ cm^-3 epilayer is investigated. Conventional one-dimensional models of BiPMOS devices are shown to overestimate the transient turn-on performance. The transient behavior of a two-dimensional BiPMOS device has been analyzed by PISCES-2B. The analysis shows that the buildup and collapse of carrier distributions induce an internal voltage overshoot and trigger substantial substrate current

Keywords

BIMOS integrated circuits; carrier density; electronic engineering computing; integrated circuit technology; semiconductor device models; transient response; 2 micron; 2D model; BiPMOS device; PISCES-2B; buried layer; carrier distributions; epilayer; internal voltage overshoot; monolithic IC; substrate current; transient turn-on performance; BiCMOS integrated circuits; Charge carrier processes; Circuit simulation; Electrostatics; Inverters; MOS devices; Parasitic capacitance; Performance analysis; Transient analysis; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on

Conference_Location

Taipei

Type

conf

DOI

10.1109/VTSA.1989.68590

Filename

68590