The 3D interconnection-an enhanced densification approach with bare chips

Author

Val, Christian

Author_Institution

Thomson-CSF, Colombes, France

fYear

1990

fDate

0-0 1990

Firstpage

82

Lastpage

91

Abstract

The author proposes interconnecting the bare chips along the Z axis rather than in the XY plane, thereby enabling a large enhancement of densification (by a factor of five to eight). This technique also substantially improves the high-frequency behavior of ICs. Inductances are very low, for example, since the longest conductor will not exceed 4.8 mm in length. In addition, the capacitances of the conductors, compared with those of the chips´ silicon lateral areas, are 10 to 100 times less than they would be with an on-polyimide thin-film interconnection. An application consisting of a cube of eight stacked 256-kb SRAMs is presented.<>

Keywords

integrated circuit technology; modules; packaging; 3D interconnection; bare chips; conductor capacitance; cube packaging; enhanced densification; high-frequency behavior; inductance; multichip module; stacked SRAMs; Area measurement; Conductors; Electronics packaging; Gold; Integrated circuit interconnections; Polymer films; Printed circuits; Semiconductor device measurement; Silicon; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Manufacturing Technology Symposium, 1990, IEMT Conference., 8th IEEE/CHMT International

Conference_Location

Baveno, Italy

Type

conf

DOI

10.1109/IEMT8.1990.171092

Filename

171092