Title :
The cost of C-testability in terms of silicon area and design complexity
Author :
Grist, D.A. ; Waller, W.A.J.
Author_Institution :
Electron. Eng. Labs., Kent Univ., Canterbury, UK
Abstract :
A comparison between C-testable and conventional CMOS implementations of a Modified Booth´s Multiplier is presented. The C-testable design which is a continuation of the work of Waller and Aziz is implemented in the DCVS logic family, and requires only 26 tests to detect all single stuck-open and stuck-closed faults. Its overhead for testability is low; only six extra inputs, two extra outputs and small amount of logic is required. However the complexity of the DCVS device is greater than that of the conventional one. Software has been developed to aid in the production of tests. The CMOS and DCVS designs where fabricated at the same time using a 1.2 micron process. The trade-offs involved in terms of area, speed and design effort are discussed in detail
Keywords :
CMOS logic circuits; fault diagnosis; logic testing; multiplying circuits; 1.2 micron; C-testability; CMOS; DCVS logic family; Si; area; design complexity; design effort; modified Booth´s multiplier; speed; stuck-closed faults; stuck-open faults;
Conference_Titel :
Systems Design for Testability, IEE Colloquium on
Conference_Location :
London
DOI :
10.1049/ic:19950549
