Reference frame access optimization for ultra high resolution H.264/AVC decoding

In an ultra high resolution H.264/AVC decoder, accessing reference frame data stored in DRAM requires huge bandwidth. The access patterns of Motion Compensation (MC) and De-blocking Filter (DF) are very different. Therefore, straightforward access and arbitration may amplify access penalty and, thus, diminish DRAM efficiency. We propose three schemes, access pattern uniformization, Macro Block (MB)-column-based mapping and task-based arbitration, to minimize the DRAM access latency including both penalty and amount of transferred data. Experimental results on a pure hardwired QFHD (3840times2160) H.264/AVC decoder system shows that by employing the proposed schemes, we achieve 86% saving in DRAM access latency.