Title :
Computing kernels implemented with a wormhole RTR CCM
Author :
Bittner, Ray A., Jr. ; Athanas, Peter M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Abstract :
The wormhole run-time reconfiguration (RTR) computing paradigm is a method for creating high performance computational pipelines. The scalability, distributed control and data flow features of the paradigm allow it to fit neatly into the configurable computing machine (CCM) domain. To date, the field has been dominated by large bit-oriented devices whose flexibility can lead to lowered silicon utilization efficiencies. In an effort to raise this efficiency, the Colt CCM has been created based on the wormhole RTR paradigm. This paper outlines methods of implementation and performance for several common operations using these concepts. They serve as indicators of the diversity of algorithms that can be instantiated through the high-speed run-time reconfiguration that these devices make possible. Particular attention is paid to floating point multiplication. Also discussed is the topic of data dependent computation which would seem to be counter intuitive to the wormhole RTR paradigm. The paper concludes with a summary of performance of the three computations
Keywords :
distributed control; field programmable gate arrays; operating system kernels; reconfigurable architectures; Colt CCM; bit-oriented devices; computing kernels; configurable computing machine; data dependent computation; data flow features; distributed control; floating point multiplication; high performance computational pipelines; high-speed run-time reconfiguration; performance; scalability; silicon utilization efficiencies; wormhole RTR CCM; wormhole run-time reconfiguration computing paradigm; Counting circuits; Data flow computing; Distributed computing; Distributed control; High performance computing; Kernel; Pipelines; Runtime; Scalability; Silicon;
Conference_Titel :
Field-Programmable Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-8186-8159-4
DOI :
10.1109/FPGA.1997.624609