Title :
Cellular semi-systolic Montgomery Multiplier on finite fields
Author :
Kim, Kee-Won ; Jeon, Jun-Cheol
Author_Institution :
Inf. Security Dept., Woosuk Univ., Jeonbuk, South Korea
Abstract :
Recently, various finite field arithmetic structures are introduced for VLSI circuit implementation on cryptosystems and error correcting codes. In this study, we present an efficient cellular semi-systolic hardware architecture for Montgomery multiplication over finite fields by choosing a proper Montgomery factor which is highly suitable for the design on parallel structures.
Keywords :
Galois fields; VLSI; digital arithmetic; error correction codes; integrated circuit design; parallel architectures; public key cryptography; systolic arrays; Montgomery factor; Montgomery multiplication; VLSI circuit implementation; cellular semisystolic Montgomery multiplier; cellular semisystolic hardware architecture; cryptosystems; error correcting codes; finite field arithmetic structures; parallel structures; Complexity theory; Computer architecture; Cryptography; Galois fields; Logic gates; Polynomials; Montgomery multiplication; cellular architecture; cryptosystem; finite field; semi-systolic;
Conference_Titel :
Cyber Security, Cyber Warfare and Digital Forensic (CyberSec), 2012 International Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4673-1425-1
DOI :
10.1109/CyberSec.2012.6246094
