Title :
Mapping applications to the RaPiD configurable architecture
Author :
Ebeling, Carl ; Cronquist, Darren C. ; Franklin, Paul ; Secosky, Jason ; Berg, Stefan G.
Author_Institution :
Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
Abstract :
The goal of the RaPiD (Reconfigurable Pipelined Datapath) architecture is to provide high performance configurable computing for a range of computationally-intensive applications that demand special-purpose hardware. This is accomplished by mapping the computation into a deep pipeline using a configurable array of coarse-grained computational units. A key feature of RaPiD is the combination of static and dynamic control. While the underlying computational pipelines are configured statically, a limited amount of dynamic control is provided which greatly increases the range and capability of applications that can be mapped to RaPiD. This paper illustrates this mapping and configuration for several important applications including a FIR filter, 2-D DCT, motion estimation, and parametric curve generation; it also shows how static and dynamic control are used to perform complex computations
Keywords :
FIR filters; discrete cosine transforms; field programmable gate arrays; motion estimation; reconfigurable architectures; 2-D DCT; FIR filter; RaPiD configurable architecture; coarse-grained computational units; complex computations; computational pipelines; deep pipeline; dynamic control; high performance configurable computing; mapping applications; motion estimation; parametric curve generation; reconfigurable pipelined datapath architecture; special-purpose hardware; Application software; Circuits; Computer architecture; Discrete cosine transforms; Field programmable gate arrays; Finite impulse response filter; Hardware; High performance computing; Motion estimation; Pipelines;
Conference_Titel :
Field-Programmable Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-8186-8159-4
DOI :
10.1109/FPGA.1997.624610