DocumentCode
2695717
Title
A 93 MHz, X86 microprocessor with on-chip L2 cache controller
Author
Draper, D. ; Crowley, M. ; Doppalapudi, U. ; McFarland, H. ; Mo, B. ; Partovi, H. ; Puziol, D. ; Scherer, A. ; Tosaya, E. ; Van Dyke, K. ; Vuong, A. ; Widigen, L. ; Yip, J. ; Yu, S. ; Roth, D.
Author_Institution
NexGen Inc., Milpitas, CA, USA
fYear
1995
fDate
15-17 Feb. 1995
Firstpage
172
Lastpage
173
Abstract
This 3.5 M-transistor microprocessor uses a 0.5 /spl mu/m CMOS technology. The die is mounted on the package with a solder-bump technology. Using custom and routed blocks with 5-layer metal, a die size of 14.1/spl times/14.1 mm/sup 2/ is produced. At 4.0 V and 25/spl deg/C, the chip operates above 93 MHz. With a 1 MB cache of 12 ns SRAMs, performance is over 120 Winstones.
Keywords
CMOS digital integrated circuits; cache storage; microprocessor chips; reduced instruction set computing; 0.5 micron; 1 MB; 12 ns; 25 C; 4 V; 5-layer metal; 93 MHz; CMOS technology; SRAM cache; X86 microprocessor; microarchitecture; on-chip L2 cache controller; solder-bump technology; CMOS technology; Clocks; Decoding; Delay; Hardware; Logic; Microprocessors; Reduced instruction set computing; Registers; Routing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-2495-1
Type
conf
DOI
10.1109/ISSCC.1995.535509
Filename
535509
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