System design for test using a genetically based hierarchical ATPG system

This paper describes a system-level hierarchical CAD test tool, which utilises the stochastic nature of genetic algorithms (GAs), expanding individual modules hierarchically and suggesting modifications to improve the testability. The GA is an artificial intelligence technique which has already been used to solve a number of problems in VLSI design and test. Optimal solutions are produced by manipulation of a population of binary strings, governed by a selection mechanism biased towards producing a superior generation. Customarily the majority of the testing procedure takes place at the gate level of abstraction within the design hierarchy, posing a problem of test vector generation that is incomplete. The proposed system has therefore been developed for integration into the hierarchical design environment, establishing a link between the architectural and gate levels of abstraction during the fault simulation procedure. The CAD tool developed will prove useful to the designer at a higher level of the design stage. This simplifies the design task, in terms of test generation at the gate level. The system also incorporates heuristics that aid the design for test strategy by suggesting insertion of controllable test points at the architectural level of abstraction. During fault simulation single stuck-at-faults are detected by initially simulating the circuit at architectural level using high level primitives. A potential fault condition within a high level primitive module, is detected by dynamically expanding it to its gate level realisation during the fault simulation function