DocumentCode
2695910
Title
A 133 MHz 64 b four-issue CMOS microprocessor
Author
Bearden, D. ; Bailey, R. ; Beavers, B. ; Gutierrez, C. ; Chin-Cheng Kau ; Lewchuk, K. ; Rossbach, P. ; Taborn, M.
Author_Institution
Somerset Design Center, Motorola Inc., Austin, TX, USA
fYear
1995
fDate
15-17 Feb. 1995
Firstpage
174
Lastpage
175
Abstract
This superscalar microprocessor is the first 64 b implementation of the PowerPC architecture. With estimated performance levels of 225 SPECint92 and 300 SPECfp92 at a nominal processor frequency of 133 MHz and a 4ML2 operating at 67 MHz, this processor delivers balanced performance suitable for high-end workstations and servers. The chip is realized in n-well 0.5 /spl mu/m CMOS with p-epi on a p/sup +/ substrate. There are four layers of metallization. The processor contains 6.88M transistors and dissipates an estimated 30 W at 133 MHz from a 3.3 V power supply. The 18.2/spl times/17.1 mm/sup 2/ die is packaged in a 25/spl times/25 ball grid array.
Keywords
CMOS digital integrated circuits; cache storage; computer architecture; content-addressable storage; microprocessor chips; pipeline processing; 0.5 micron; 133 MHz; 64 bit; 67 MHz; BGA package; PowerPC architecture; ball grid array; four-issue CMOS microprocessor; n-well CMOS process; superscalar microprocessor; Buffer storage; CADCAM; Cams; Clocks; Computer aided manufacturing; Decoding; History; Microprocessors; Pipelines; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-2495-1
Type
conf
DOI
10.1109/ISSCC.1995.535510
Filename
535510
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