On the effect of spare positioning on the reconfigurability of two-dimensional processor arrays

We investigated some reconfiguration and routing aspects of fault tolerant processing arrays. An interconnection topology with disjoint buses for the horizontal and vertical connections, called “double bus array”, was adopted. Reconfiguration of the array after diagnosis encompasses the allocation of spare units to replace the faulty processors, renaming of the processor elements and interconnecting (routing) data through the operating processors according to the initial specified operation. We fully simulated reconfiguration and routing for arrays of size N, from 5 to 25 processors and faults from 1 to 2N+1. Faults were generated randomly to simulate defects on a wafer. We present the results of the simulations and discuss the possible reasons for reliability improvements