Silicon interconnect-a critical factor in device thermal management

Analytical and experimental methodologies for studying silicon device degradation under electrothermal stress are discussed. The experimental data support the assumption that the thermally induced stress due to power cycling and power surges is a major cause of device degradation. The analytical models point out the large impact that low-thermal-diffusivity layers (solder or epoxy) located near the heat source (the thermal junction) have on the acceleration of fatigue phenomena. Crack initiation and propagation in die attach layers due to stress/strain cycles is shown to be one of the leading factors in degradation of power cycled devices. It is concluded that correct design or selection of the silicon device interconnect can increase device reliability and allow the device to operate at temperatures up to 125°C, without increasing the field failure rate. The data in this study were accumulated during the investigation of failure mechanisms of solid-state protection devices. The nature of the observed degradation mechanism indicates that the conclusions can be extrapolated to the degradation mechanism of common logic devices (bipolar or MOS)