Dependence of the negative bias temperature instability on the gate oxide thickness

The exact location and type of defects created under negative bias temperature (NBT) stress in pMOS field effect transistors is still a highly debated topic. We present a detailed study on equivalent devices with different oxide thicknesses (5 to 30 nm) where we show experimentally that the basic mechanisms behind the NBT instability are the same in thin and thick oxide technologies. In particular, voltage driven degradation like impact ionization or anode hole injection are not the driving forces for the larger degradation of thick oxide devices. Finally, we show that defects created under NBT stress are not solely located at the interface but extend a few nanometers into the oxide.