Allowing cycle-stealing direct memory access I/O concurrent with hard-real-time programs

Hard-real-time schedulability analysis is carried out based on the assumption that the worst-case execution time (WCET) of each task is known. Cycle-stealing Direct Memory Access (DMA) I/O steals bus cycles from an executing program and prolongs the execution time of the program. Because of the difficulty in bounding the interference on the executing program, cycle-stealing DMA I/O is often disabled in hard-real-time systems. This paper presents an analytical method for bounding the WCET of a program executing concurrently with cycle-stealing DMA I/O. This is an extension of our previous work which bounded the WCET of a straight-line sequence of instructions when cycle-stealing operations are allowed. We demonstrate the effectiveness of our method with experiments on several programs